1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a ball grid array package with stacked center pad chips, which realizes a stacked package of a Fine Ball Grid Array (FBGA) type by stacking more than one center pad type semiconductor chips, and a method for manufacturing the same.
2. Description of the Prior Art
In the semiconductor industry, packaging technology for IC chips is continuously progressing in order to meet the desire for compactness and improved mounting reliability. Furthermore, as the performance of electronic devices is getting better, efforts have been made to mount a larger number of semiconductor packages on a substrate having a limited size. As a result of such efforts, there has been proposed a so-called “stacked package”.
The stacked package was devised in order to increase memory capacity by stacking memory chips of a same size and function or to maximize the performance and efficiency of products by assembling various kinds of semiconductor chips with different size and function. There are many types of stacked packages according to the corresponding end-use products, makers, etc. One example of stacked packages according to the prior art is illustrated in FIG. 1.
The stacked package shown in FIG. 1 belongs to a package-stacking type. In other words, the stacked package is constructed by stacking individual packages 11, 12 and classified as a Thin Small Outline Package (TSOP) type. Each of the individual packages 11, 12 in FIG. 1 comprises a semiconductor chip 13 therein and uses a Lead-on-Chip (LOC) lead frame. The lead frame has an internal lead 14 glued on the upper surface of the semiconductor chip 13 by an adhesive tape 15 and connected therewith electrically by a gold wire 16. The stacked packages 11, 12 are connected together electrically by a separate connecting lead 17. The connecting lead 17 is joined to each outer lead 18 of the respective lead frames and acts as an outer connection terminal of the stacked package 10.
However, because of their large mounting area and considerable height, stacked packages 10, as mentioned above, are hardly applicable to such systems as information communication devices, which require compactness and thinness. They are not suitable for high-speed devices either, since they use lead frames 14, 17, 18. Moreover, as the path between a mounting point and the semiconductor chip 14 of the upper package 12 is longer than the path between the mounting point and the semiconductor chip 13 of the lower package 11, there exists a difference in electrical characteristics.
Accordingly, a Ball Grid Array (BGA) package using solder balls as outer connection terminals has been proposed, for the purpose of improving electrical characteristics by minimizing both the surface mounting area of a semiconductor package and the electrical connection length thereof. Referring to FIG. 2, there is illustrated a so-called “BGA package with stacked chips”, which has been basically configured as a BGA package and has semiconductor chips stacked therein.
As shown in FIG. 2, individual semiconductor chips 23, 24 are stacked within the package mold 27 of the BGA package with stacked chips 20. Instead of lead frames, a printed circuit board (PCB) 21 and solder balls 28 are used in the package 20. The lower semiconductor chip 23 is glued on the PCB 21 having wirings 22 attached thereon with adhesives 25, and then the upper semiconductor chip 24 is glued on the lower semiconductor chip 23. Each of the semiconductor chips 23, 24 is connected electrically with the wirings 22 of the PCB 21 by means of gold wires 26. The PCB 21 is provided with solder balls 28 on its lower surface for electrical connection with the wirings 22. The solder balls 28 act as outer connection terminals for the package 20.
However, the BGA packages with stacked chips, as explained above, can use nothing but semiconductor chips of a so-called “side pad type”. On the active surfaces of semiconductor chips such as DRAM chips, a number of chip pads 23a, 24a are formed for performing input/output with external elements. If the chip pads 23a, 24a are formed on the edges of the active surfaces of semiconductor chips, the chips are said to be semiconductor chips of the side pad type 23, 24.
Recently, a semiconductor chip of a so-called “center pad type” has been generalized, having chip pads formed along the center of active surfaces of the chips, since the center pad type is more advantageous for implementation in a high speed device. Meanwhile, BGA packages with stacked chips 20 according to the prior art, as shown in FIG. 2, have a defect in that they cannot use center pad type semiconductor chips because of the difficulty in stacking chips and the increased length of gold wires. BGA packages with stacked chips 20 are also vulnerable to a warpage phenomenon, since thermal stress can become concentrated in the upper portion of the package.
As a result, only one center pad type semiconductor chip can be implemented in a BGA package, according to the prior art. An example of a BGA package with a center pad chip is illustrated in FIG. 3.
As illustrated in FIG. 3, a BGA package with a center pad chip 30 is constructed by gluing the active surface of a semiconductor chip 32, having a chip pad 32a formed thereon, on a circuit board 31 and connecting the semiconductor chip 32 with the circuit board 31 using gold wires 33. A package mold 34 protects the semiconductor chip 32 and the gold wires 33. Solder balls 35, acting as outer connection terminals, are formed on the circuit board 31.
As explained above, stacked packages, BGA packages and center pad type semiconductor chips all have their own advantages. However, it has been considered very difficult to implement a package that combines all the advantages of the stacked packages, BGA packages and center pad type semiconductor chips, from the viewpoint of structure, manufacturing cost and process stability.